1. Technical Field
The disclosure relates in general to a semiconductor structure and a method for manufacturing the same, and more particularly to the semiconductor structure and method for separately manufacturing an array region and a periphery region on different chips.
2. Description of the Related Art
FIG. 1 illustrates a conventional chip. The conventional chip includes an array region 10 and a periphery region 20. The array region 10 includes plural parallel bit lines 103 and plural parallel word lines 101 intersected to each other, to form a memory array. The word lines 101 and the bit lines 103 are electrical connected to the periphery region 20 by the contacts 101c, 103c. The periphery region 20 could include different circuit types, such as WL decoder 201 and the BL page buffer 203.
If Cp represents process cost per area of chip, Cp=Cpa+Cpp, Cpa represents process cost per area of array region, Cpp represents process cost per area of periphery region. A is total area of chip. A=Aa+Ap, Aa is area of the array region, and Ap is area of the periphery region. Thus the total cost C =Cp×A=(Cpa+Cpp)×(Aa+Ap)=Cpa×Aa+Cpa×Ap+Cpp×Aa+Cpp×Ap. If the periphery region could be fabricated separately on another chip, the items Cpa×Ap and Cpp×Aa can be removed, and the total cost C could be decreased.
Moreover, the chip size has been reduced, and the feature size of components in the chip, and the areas of the array region and the periphery region have been shrunk, and also the density of word lines 101 and bit lines 103 has been increased. The distances between the contacts 101c and 103c at the ends of the word lines 101 and bit lines 103 become very small. It would be very difficult to connect those contacts 101c and 103c to other chips. Although the adjacent contacts 101c/103c may space apart along the x/y direction to decrease the possibility of short circuit, a certain area is still required for setting those contacts 101c and 103c, thereby limiting the extent of the chip size reduction.